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The HDL Lola and its Translation to Verilog

Dept. of Computer Science (January 27, 2015)

SEMINAR SERIES : Distinguished lecture

MAJOR SPEAKER : Wirth, Niklaus
LENGTH : 59 min.
ACCESS : Open to all
SUMMARY : Electronic circuits used to be specified by diagrams which more or less represented their physical layout. As circuits became very complex, the limitations of diagrams became apparent. Over time, they were replaced by textual descriptions, giving rise to Hardware Description Languages (HDL). One of the prominent HDLs is Verilog, closely mirroring the appearance of C. Around 1990 we designed the HDL Lola adopting the same goals as for the PL Oberon: A simple and economical vehicle for teaching. The effort was encouraged by the advent of FPGAs, re-configurable components. We implemented Lola for the FPGAs of Concurrent Logic and of Algotronics, which since then have vanished. Now we have unearthed and revived Lola and built a compiler. But unlike before, its output is not a configuration file to be loaded onto the chip, but a translation into Verilog. Here we present the gist of Lola-2 and its compiler. Finally we ponder about the differences between HDLs and PLs in general. Are they fundamental? And what are they?  [Go to the full record in the library's catalogue]

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