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Distinguished lecture (Hong Kong Baptist University. Dept. of Computer Science)

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The HDL Lola and its Translation to Verilog

DEPARTMENT:

Department of Computer Science

CONYTRIBUTOR / SPEAKER:

WIRTH, Niklaus

RELEASE DATE:

2015

LENGTH:

59 Minutes

VIDEO TYPE:

Scholarly Talks

Electronic circuits used to be specified by diagrams which more or less represented their physical layout. As circuits became very complex, the limitations of diagrams became apparent. Over time, they were replaced by textual descriptions, giving rise to Hardware Description Languages (HDL). One of the prominent HDLs is Verilog, closely mirroring the appearance of C. Around 1990 we designed the HDL Lola adopting the same goals as for the PL Oberon: A simple and economical vehicle for teaching. The effort was encouraged by the advent of FPGAs, re-configurable components. We implemented Lola for the FPGAs of Concurrent Logic and of Algotronics, which since then have vanished. Now we have unearthed and revived Lola and built a compiler. But unlike before, its output is not a configuration file to be loaded onto the chip, but a translation into Verilog. Here we present the gist of Lola-2 and its compiler. Finally we ponder about the differences between HDLs and PLs in general. Are they fundamental? And what are they?

The HDL Lola and its Translation to Verilog

部門:

計算機科學系

講者:

WIRTH, Niklaus

發佈日期:

2015

影片長度:

59 分鐘

影片類型:

學術論壇

The HDL Lola and its Translation to Verilog

部门:

计算机科学系

讲者:

WIRTH, Niklaus

发布日期:

2015

影片长度:

59 分钟

影片类型:

学术论坛

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